1. Field of the Invention
The present invention relates to a semiconductor device and a method for manufacturing the same. More particularly, the present invention relates to a semiconductor device which is formed with a low resistance metal suicide layer having a superior phase stability and to a method for manufacturing the metal silicide layer.
2. Description of the Related Art
As semiconductor devices become more highly integrated, the design rule of a device, such as channel length, an interval between the active areas, a wiring width, a wiring interval, and a contact size of a transistor are scaled-down. Regarding the contact size of a transistor, a silicidation process for forming a metal suicide is carried out in order to obtain a low resistance contact. Reducing the size of the contact causes the thickness uniformity of a silicide layer and the step coverage of the silicide layer to be of inferior quality.
Conventionally, the metal silicide layer is formed on a bottom of a contact hole or a via hole using an argon sputtering process and an evaporation process using an electronic beam. However, use of those processes results in less step coverage than if a CVD (chemical vapor deposition) process is used. Additionally, it is difficult to uniformly control the thickness of the silicide layer.
When the metal silicide layer is formed using the CVD process, silicon etching can occur depending on the vacuum levels caused by the source gas which is deposited at a high temperature. In addition, the isotropic deposition feature can cause undesired metal deposition at sidewalls of the contact hole or the via hole. Accordingly, the silicon deposited on the bottom of the contact hole reacts with the metal deposited on the sidewalls of the contact hole. In this case, the silicon is over-consumed, so bulk depletion and voids are generated, which cause contact resistance failure. In addition, the step coverage may be reduced depending on the aspect ratio of the contact hole when the silicide layer is formed using the CVD process.
U.S. Pat. No. 5,780,929 discloses a method for forming a defect enhanced cobalt silicide layer. According to the disclosure of the above-referenced U.S. patent, a silicon substrate is defected by implanting argon into the silicon substrate without performing a separate heat treatment process. However, it is difficult to defect the silicon substrate properly, so the defection remaining on a surface of the silicon substrate can act as a source of current leakage. In addition, since the resistance is increased due to the argon implanted into the silicon substrate, the resistance reducing effect of a shallow silicide layer is reduced when a shallow junction is formed using the above method.
On the other hand, as the design rule of the device is scaled down, a margin is required with respect to a short channel effect and a punch-through of the transistor. Accordingly, forming a shallow junction of a source/drain area and reducing the parasitic resistance, such as a sheet resistance and a contact resistance, of the source/drain area are required. For this reason, a self-aligned silicide (hereinafter, referred to as xe2x80x9csalicidexe2x80x9d) process has been developed, in which the silicide is selectively formed on a surface of a gate and a surface of a source/drain area to reduce the non-resistance of the gate, and the sheet resistance and contact resistance of the source/drain area.
According to a conventional salicide process, a metal layer is deposited in a sputtering method. Then a first heat-treatment process is carried cut to form a metal silicide layer having a first phase. Non-reacted metal layers are selectively removed by a wet etching process. Then, a second heat-treatment process is carried out to form a metal silicide layer having a second phase, which is stable with respect to the resistance and the phase stability as compared with the metal silicide having the first phase. However, the conventional salicide process does not uniformly form a shallow silicide layer having a thickness of less than 400 xc3x85, which is problematic. When a silicide layer having a thickness of greater than 400 xc3x85 is formed, the uniformity of thickness and the uniformity of the surface roughness are reduced. Furthermore, the distance between the junction portion and the silicide layer is irregularly formed making it difficult to preserve the junction. For example, if the salicide process is carried out after depositing a cobalt layer having a thickness of greater than 100 xc3x85, the thickness difference of a cobalt disilicide layer (CoSi2) having a thickness of 300 to 400 xc3x85 is greater than xc2x1150 xc3x85. In addition, since the heat-treatment process is carried out twice, the high heat budget can cause the agglomeration of the metal silicide layer and lateral over-growing.
In order to solve the aforementioned problems, a process for forming an epitaxial suicide layer has been suggested. However, this process requires a monocrystalline silicon seed and therefore, is not adapted for the polycrystalline silicon layer. In addition, the vacuum level of the process chamber has to be maintained below 1E-10 torr in order to obtain reproducibility. Furthermore, the deposition speed and the throughput are reduced; hence, it is not adapted for mass-production.
In order to solve the aforementioned problems, it is a feature of an embodiment of the present invention to provide a semiconductor device which achieves a low contact resistance by forming an ohmic contact with respect to a semiconductor layer by using a metal silicide thin film.
Another feature of an embodiment of the present invention is to provide a method for forming a low resistance metal silicide having a high phase stability by using native metal silicide formed at an interfacial area between metal and silicon.
Still another feature of an embodiment of the present invention is to provide a method for forming a metal silicide layer in a semiconductor device, in which a salicide process can be achieved by using native metal silicide formed at an interfacial area between metal and silicon.
In an embodiment of the present invention, there is provided a semiconductor device having a metal silicide-semiconductor contact structure, the semiconductor device comprising: a substrate; an insulation layer having an opening formed on the substrate; a metal silicide layer formed in the opening of the insulation layer, by using a native metal suicide having a first phase, the metal silicide layer having a second phase which has a first stoichiometrical composition ratio that is different from a second stoichiometrical composition ratio of the first phase; a conductive layer formed on the metal silicicle layer of the second phase, wherein the metal suicide layer is formed between the substrate and the conductive layer and the metal suicide layer has a thickness of less than about 100 xc3x85.
In another embodiment of the present invention, there is provided a method for forming a metal suicide layer in a semiconductor device comprising: i) providing a substrate; ii) forming an insulation layer on the substrate, the insulation having an opening therein; iii) depositing a metal in the opening of the insulation layer so that a first layer including a native metal silicide layer of a first phase is formed at an interfacial area between the substrate and the deposited metal; iv) selectively removing the first layer while retaining the native metal silicide layer of the first phase; v) forming a second layer made of a conductive material on the native metal silicide layer of the first phase and the insulation layer; and vi) reacting the native metal silicide layer of the first phase with the substrate in order to transform the native metal silicide layer into a metal silicide layer having a second phase which has a first stoichiometrical composition ratio that is different from a second stoichiometrical composition ratio of the first phase.
In still another embodiment of the present invention, there is provided a method for forming a metal silicide layer in a semiconductor device comprising: i) providing a substrate having formed thereon a gate oxide film and a gate stack including a conductive material including silicon and having gate sidewall spacers on sides thereof; ii) depositing a metal on the substrate, the gate stack and the gate sidewall spacers, in such a manner that a first layer including a native metal silicide layer of a first phase is formed at an interfacial area between the silicon and the deposited refractory metal; iii) selectively removing the first layer while retaining the native metal silicide layer of the first phase; iv) depositing a first capping layer on a resulting structure; and v) reacting the native metal silicide layer of the first phase with the silicon in order to transform the native metal silicide layer into a metal silicide layer having a second phase which has a first stoichiometrical composition ratio that is different from a second stoichiometrical composition ratio of the first phase and a thickness of less than about 100 xc3x85.
According to yet another embodiment of the present invention, by using the native metal silicide formed at an interfacial area between the metal and the silicon, the native metal silicide layer is reacted with the silicon by means of a heat-treatment process so that a metal silicide layer with high phase stability and low resistance is obtained. Therefore, a thin metal silicide layer is uniformly If formed, and the stepped portion is uniformly coated with the thin metal silicide layer. Additionally, when an embodiment of the present invention is applied to the salicide process, the primary heat-treatment process can be skipped so that the heat budget is reduced. Accordingly, the process is simplified and a shallow junction may be achieved.
These and other features of the present invention will be readily apparent to those of ordinary skill in the art upon review of the detailed description that follows.